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FS23 Scheda tecnica(PDF) 137 Page - NXP Semiconductors

Il numero della parte FS23
Spiegazioni elettronici  Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers
PDF  230 Pages
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Produttore elettronici  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS23 Scheda tecnica(HTML) 137 Page - NXP Semiconductors

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NXP Semiconductors
FS23
Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers
Bit
Symbol
Description
Report HVIO2 wake-up event
0 No wake-up by HVIO2 (level) or HVIO2 pin state did not change between two trigger event (cyclic sense)
1 Wake up by HVIO2 occurred (level) or HVIO2 pin state changed between two trigger event (cyclic sense)
7
HVIO2_WU_I
POR or fail-safe or clear on write (write '1)
Report HVIO1 state at trigger point
0 State at trigger point captured at 0
1 State at trigger point captured at 1
8
HVIO1_CYC_S
POR, or each trigger point
Report HVIO2 state at trigger point
0 State at trigger point captured at 0
1 State at trigger point captured at 1
9
HVIO2_CYC_S
POR, or each trigger point
Report HVIO1 readiness for cyclic sense
0 Cyclic sense not ready
1 Cyclic sense ready
10
HVIO1_CYS_RDY
POR
Report HVIO2 readiness for cyclic sense
0 Cyclic sense not ready
1 Cyclic sense ready
11
HVIO2_CYS_RDY
POR
Report LVIO3 wake-up event (outside Normal mode)
0 no wake-up by LVIO3
1 wake-up by LVIO3 occurred
13
LVIO3_WU_I
POR or fail-safe or clear on write (write '1)
Report LVIO4 wake-up event (outside Normal mode)
0 no wake-up by LVIO4
1 wake-up by LVIO4 occurred
14
LVIO4_WU_I
POR or fail-safe or clear on write (write '1)
Report LVI5 wake-up event (outside Normal mode)
0 no wake-up by LVI5
1 wake-up by LVI5 occurred
15
LVI5_WU_I
POR or fail-safe or clear on write (write '1)
Table 112. M_IOWU_FLG register bit description...continued
22.20 M_WU1_EN
Bit
15
14
13
12
11
10
9
8
Write
-
-
-
-
-
-
-
-
Read
0
0
0
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Write
-
-
LDT_WUEN
LIN_WUEN
CAN_WUEN
Read
0
0
LDT_WUEN
LIN_WUEN
CAN_WUEN
Reset
0
0
0
0
1
1
1
1
Table 113. M_WU1_EN register bit allocation
FS23
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 7.0 — 16 October 2024
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