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FS23 Scheda tecnica(PDF) 141 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 141 Page - NXP Semiconductors |
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141 / 230 page ![]() NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers 22.23 M_TIMER2_CFG Bit 15 14 13 12 11 10 9 8 Write - - - - - - - TIMER2_DLY Read 0 0 0 0 0 0 0 TIMER2_DLY Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Write TIMER2_DLY TIMER2_ON TIMER2_PER Read TIMER2_DLY TIMER2_ON TIMER2_PER Reset 0 0 0 0 0 0 0 0 Table 119. M_TIMER2_CFG register bit allocation Bit Symbol Description Configure the TIMER2 period 000 TIMER2 period = 10.24 ms 001 TIMER2 period = 20.48 ms 010 TIMER2 period = 51.2 ms 011 TIMER2 period = 102.4 ms 100 TIMER2 period = 204.8 ms 101 TIMER2 period = 512 ms 110 TIMER2 period = 1024 ms 111 TIMER2 period = 2048 ms 0 to 2 TIMER2_PER POR Configure the TIMER2 ON time 0000 TIMER2 ON time = 0 ms 0001 TIMER2 ON time = 0.128 ms 0010 TIMER2 ON time = 0.256 ms 0011 TIMER2 ON time = 1.024 ms 0100 TIMER2 ON time = 10.24 ms 0101 TIMER2 ON time = 20.48 ms 0110 TIMER2 ON time = 30.72 ms 0111 TIMER2 ON time = 40.96 ms 1000 TIMER2 ON time = 51.2 ms 1001 TIMER2 ON time = 61.44 ms 1010 TIMER2 ON time = 81.92 ms 1011 TIMER2 ON time = 102.4 ms 1100 TIMER2 ON time = 122.88 ms 1101 TIMER2 ON time = 153.6 ms 1110 TIMER2 ON time = 204.8 ms 1111 TIMER2 ON time = Infinite 3 to 6 TIMER2_ON POR Table 120. M_TIMER2_CFG register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 141 / 230 |
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