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FS23 Scheda tecnica(PDF) 140 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 140 Page - NXP Semiconductors |
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140 / 230 page ![]() NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers Bit Symbol Description Configure the TIMER1 period 000 TIMER1 period = 10.24 ms 001 TIMER1 period = 20.48 ms 010 TIMER1 period = 51.2 ms 011 TIMER1 period = 102.4 ms 100 TIMER1 period = 204.8 ms 101 TIMER1 period = 512 ms 110 TIMER1 period = 1024 ms 111 TIMER1 period = 2048 ms 0 to 2 TIMER1_PER POR Configure the TIMER1 ON time 0000 TIMER1 ON time = 0 ms 0001 TIMER1 ON time = 0.128 ms 0010 TIMER1 ON time = 0.256 ms 0011 TIMER1 ON time = 1.024 ms 0100 TIMER1 ON time = 10.24 ms 0101 TIMER1 ON time = 20.48 ms 0110 TIMER1 ON time = 30.72 ms 0111 TIMER1 ON time = 40.96 ms 1000 TIMER1 ON time = 51.2 ms 1001 TIMER1 ON time = 61.44 ms 1010 TIMER1 ON time = 81.92 ms 1011 TIMER1 ON time = 102.4 ms 1100 TIMER1 ON time = 122.88 ms 1101 TIMER1 ON time = 153.6 ms 1110 TIMER1 ON time = 204.8 ms 1111 TIMER1 ON time = Infinite 3 to 6 TIMER1_ON POR Configure the TIMER1 delay time (apply on rising edge only) 00 TIMER1 delay = 0 us 01 TIMER1 delay = 5 us 10 TIMER1 delay = 10 us 11 TIMER1 delay = 15 us 7 to 8 TIMER1_DLY POR Table 118. M_TIMER1_CFG register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 140 / 230 |
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