H8SSLASH2214 datasheet(638/936 Pages) RENESAS

638 / 936 page

Section 15 ROM

Rev.4.00 Sep. 18, 2008 Page 578 of 872

REJ09B0189-0400

15.10.3 Error Protection

In error protection, an error is detected when LSI runaway occurs during flash memory

programming/erasing, or operation is not performed in accordance with the program/erase

algorithm, and the program/erase operation is aborted. Aborting the program/erase operation

prevents damage to the flash memory due to overprogramming or overerasing.

If the LSI malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in

FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2

settings are retained, but program mode or erase mode is aborted at the point at which the error

occurred. Program mode or erase mode cannot be re-entered by re-setting the P1 or E1 bit.

However, PV1 and EV1 bit setting is enabled, and a transition can be made to verify mode.

FLER bit setting conditions are as follows:

1. When the flash memory of the relevant address area is read during programming/erasing

(including vector read and instruction fetch)

2. Immediately after exception handling (excluding a reset) during programming/erasing

3. When a SLEEP instruction (including software standby) is executed during

programming/erasing

4. When the CPU releases the bus to the DTC during programming/erasing.

Error protection is released only by a power-on reset and in hardware standby mode.

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