ATtiny261A datasheet(72/292 Pages) ATMEL

72 / 292 page

8197A–AVR–10/09

ATtiny261A/461A/861A

Figure 11-3. T0 Pin Sampling

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles

from an edge has been applied to the T0 pin to the counter is updated.

Enabling and disabling of the clock input must be done when T0 has been stable for at least one

system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

Each half period of the external clock applied must be longer than one system clock cycle to

ensure correct sampling. The external clock must be guaranteed to have less than half the sys-

tem clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses

sampling, the maximum frequency of an external clock it can detect is half the sampling fre-

quency (Nyquist sampling theorem). However, due to variation of the system clock frequency

and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is

recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5.

An external clock source can not be prescaled.

11.4 Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

11-4 shows a block diagram of the counter and its surroundings.

Table 11-2.

Counter Unit Block Diagram

Signal description (internal signals):

count

Increment or decrement TCNT0 by 1.

clkTn

Timer/Counter clock, referred to as clkT0 in the following.

top

Signalize that TCNT0 has reached maximum value.

The counter is incremented at each timer clock (clkT0) until it passes its TOP value and then

restarts from BOTTOM. The counting sequence is determined by the setting of the CTC0 bit

located in the Timer/Counter Control Register (TCCR0A). For more details about counting

sequences, see “Modes of Operation” on page 75. clkT0 can be generated from an external or

Tn_sync

(To Clock

Select Logic)

Edge Detector

Synchronization

clk

I/O

DATA BUS

TCNTn

Control Logic

count

TOVn

(Int.Req.)

Clock Select

top

Edge

Detector

( From Prescaler )

clk

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