ATtiny261A datasheet(85/292 Pages) ATMEL

85 / 292 page

8197A–AVR–10/09

ATtiny261A/461A/861A

if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the

Timer/Counter 0 Interrupt Flag Register – TIFR0.

• Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable

When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if

a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter

Interrupt Flag Register – TIFR0.

• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Inter-

rupt Flag Register – TIFR0.

• Bit 0 – TICIE0: Timer/Counter0, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt

Vector (See “Interrupts” on page 48.) is executed when the ICF0 flag, located in TIFR, is set.

11.10.8

TIFR – Timer/Counter0 Interrupt Flag Register

• Bit 4– OCF0A: Output Compare Flag 0 A

The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data

in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the cor-

responding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to

the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable),

and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.

The OCF0A is also set in 16-bit mode when a Compare Match occurs between the Timer/Coun-

ter and 16-bit data in OCR0B/A. The OCF0A is not set in Input Capture mode when the Output

Compare Register OCR0A is used as an Input Capture Register.

• Bit 3 – OCF0B: Output Compare Flag 0 B

The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in

OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the cor-

responding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to

the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable),

and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.

The OCF0B is not set in 16-bit Output Compare mode when the Output Compare Register

OCR0B is used as the high byte of the 16-bit Output Compare Register or in 16-bit Input Cap-

ture mode when the Output Compare Register OCR0B is used as the high byte of the Input

Capture Register.

Bit

76543210

0x38 (0x58)

OCF1D

OCF1A

OCF1B

OCF0A

OCF0B

TOV1

TOV0

ICF0

TIFR

Read/Write

R/W

Initial Value

00000000

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