ATtiny261A datasheet(27/292 Pages) ATMEL

27 / 292 page

8197A–AVR–10/09

ATtiny261A/461A/861A

The fast peripheral clock, clkPCK, can be selected as the clock source for Timer/Counter1 and a

prescaled version of the PLL output, clkPLL, can be selected as system clock. See Figure 6-3 for

a detailed illustration on the PLL clock system.

Figure 6-3.

PCK Clocking System

The internal PLL is enabled when CKSEL fuse bits are programmed to ‘0001’and the PLLE bit of

PLLCSR is set. The internal oscillator and the PLL are switched off in power down and stand-by

sleep modes.

When the LSM bit of PLLCSR is set, the PLL switches from using the output of the internal 8

MHz oscillator to using the output divided by two. The frequency of the fast peripheral clock is

effectively divided by two, resulting in a clock frequency of 32 MHz. The LSM bit can not be set if

PLLCLK is used as a system clock.

Since the PLL is locked to the output of the internal 8 MHz oscillator, adjusting the oscillator fre-

quency via the OSCCAL register also changes the frequency of the fast peripheral clock. It is

possible to adjust the frequency of the internal oscillator to well above 8 MHz but the fast periph-

eral clock will saturate and remain oscillating at about 85 MHz. In this case the PLL is no longer

locked to the internal oscillator clock signal. Therefore, in order to keep the PLL in the correct

operating range, it is recommended to program the OSCCAL registers such that the oscillator

frequency does not exceed 8 MHz.

The PLOCK bit in PLLCSR is set when PLL is locked.

Programming CKSEL fuse bits to ‘0001’, the PLL output divided by four will be used as a system

clock, as shown in Table 6-4.

Table 6-4.

PLLCK Operating Modes

CKSEL3:0

Nominal Frequency

0001

16 MHz

1/2

8 MHz

LSM

8 MHz

OSCILLATOR

PLL

CKSEL3:0

PLLE

OSCCAL

4 MHz

1/4

LOCK

DETECTOR

PRESCALER

CLKPS3:0

clkPLL

PLOCK

clkPCK

OSCILLATORS

XTAL1

XTAL2

64 / 32 MHz

8 MHz

16 MHz

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