ATtiny261A datasheet(91/292 Pages) ATMEL

91 / 292 page

8197A–AVR–10/09

ATtiny261A/461A/861A

12.3.1.1

Prescaler Reset

Setting the PSR1 bit in TCCR1B register resets the prescaler. It is possible to use the Prescaler

Reset for synchronizing the Timer/Counter to program execution.

12.3.1.2

Prescaler Initialization for Asynchronous Mode

To change Timer/Counter1 to the asynchronous mode follow the procedure below:

1. Enable PLL.

2. Wait 100 µs for PLL to stabilize.

3. Poll the PLOCK bit until it is set.

4. Set the PCKE bit in the PLLCSR register which enables the asynchronous mode.

12.4 Counter Unit

The main part of the Timer/Counter1 is the programmable bi-directional counter unit. Figure 12-

4 shows a block diagram of the counter and its surroundings.

Figure 12-4. Counter Unit Block Diagram

Signal description (internal signals):

count

TCNT1 increment or decrement enable.

direction

Select between increment and decrement.

clear

Clear TCNT1 (set all bits to zero).

clkTn

Timer/Counter clock, referred to as clkT1 in the following.

top

Signalize that TCNT1 has reached maximum value.

bottom

Signalize that TCNT1 has reached minimum value (zero).

Depending on the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clkT1). The timer clock is generated from an synchronous system clock or an

asynchronous PLL clock using the Clock Select bits (CS13:0) and the PCK Enable bit (PCKE).

When no clock source is selected (CS13:0 = 0) the timer is stopped. However, the TCNT1 value

can be accessed by the CPU, regardless of whether clkT1 is present or not. A CPU write over-

rides (has priority over) all counter clear or count operations.

The counting sequence of the Timer/Counter1 is determined by bits WGM11:10, PWM1A and

PWM1B, located in the Timer/Counter1 Control Registers (TCCR1A, TCCR1C and TCCR1D).

For more details about advanced counting sequences and waveform generation, see “Modes of

Operation” on page 97. The Timer/Counter Overflow Flag (TOV1) is set according to the mode

of operation and can be used for generating a CPU interrupt.

DATA BUS

TCNT1

Control Logic

count

TOV1

top

Timer/Counter1 Count Enable

( From Prescaler )

bottom

direction

clear

PCK

PCKE

clk

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