ATtiny261A datasheet(90/292 Pages) ATMEL

90 / 292 page

8197A–AVR–10/09

ATtiny261A/461A/861A

counter value and so on. The definitions in Table 12-1 are used extensively throughout the

document.

12.3 Clock Sources

The Timer/Counter is clocked internally, either from CK or PCK. See bits CSxx in Table 12-17 on

page 114 and bit PCKE in “PLLCSR – PLL Control and Status Register” on page 118.

12.3.1

Prescaler

Figure 12-3 shows the Timer/Counter1 prescaler that supports two clocking modes, a synchro-

nous clocking mode and an asynchronous clocking mode. The synchronous clocking mode uses

the system clock (CK) as a clock timebase and asynchronous mode uses the fast peripheral

clock (PCK) as a clock time base. The PCKE bit from the PLLCSR register enables the asyn-

chronous mode when it is set (‘1’).

Figure 12-3. Timer/Counter1 Prescaler

In the asynchronous clocking mode the clock selections are from PCK to PCK/16384 and stop,

and in the synchronous clocking mode the clock selections are from CK to CK/16384 and stop.

The clock options are illustrated in Figure 12-3 and desribed in “TCCR1B – Timer/Counter1

Control Register B” on page 113.

The frequency of the fast peripheral clock is 64 MHz or 32 MHz in Low Speed mode (the LSM bit

in PLLCSR register is set to one). The Low Speed Mode is recommended to use when the sup-

ply voltage below 2.7 volts are used.

Table 12-1.

Definitions

Constant

Description

BOTTOM

The counter reaches BOTTOM when it becomes 0x00

MAX

The counter reaches its MAXimum when it becomes 0xFF (decimal 255)

TOP

The counter reaches the TOP when it becomes equal to the highest value in the count

sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the

value stored in the OCR0A Register. The assignment depends on the mode of operation

TIMER/COUNTER1 COUNT ENABLE

PSR1

CS10

CS11

CS12

PCK 64/32 MHz

CS13

14-BIT

T/C PRESCALER

PCKE

T1CK

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