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ATtiny261A Scheda tecnica(PDF) 52 Page - ATMEL Corporation |
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ATtiny261A Scheda tecnica(HTML) 52 Page - ATMEL Corporation |
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52 / 292 page ![]() 52 8197A–AVR–10/09 ATtiny261A/461A/861A When a logic change on any PCINT15 pin triggers an interrupt request, PCIF becomes set (one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the cor- responding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. • Bits 4:0 – Res: Reserved Bits These bits are reserved and will always read as zero. 9.3.4 PCMSK0 – Pin Change Mask Register A • Bits 7:0 – PCINT7:0: Pin Change Enable Mask 7:0 Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on the cor- responding I/O pin. If PCINT7:0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 9.3.5 PCMSK1 – Pin Change Mask Register B • Bits 7:0 – PCINT15:8: Pin Change Enable Mask 15:8 Each PCINT15:8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT11:8 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin, and if PCINT15:12 is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corresponding I/O pin is disabled. Bit 7654 3210 0x23 (0x43) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0 Read/Write R/W R/W R/W R/w R/W R/W R/W R/W Initial Value 1100 1000 Bit 7654 3210 0x22 (0x42) PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 PCMSK1 Read/Write R/W R/W R/W R/w R/W R/W R/W R/W Initial Value 1111 1111 |
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