ATtiny261A datasheet(76/292 Pages) ATMEL

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8197A–AVR–10/09

ATtiny261A/461A/861A

The Overflow Flag (TOV0) is set in the same timer clock cycle as when TCNT0L becomes zero.

The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. How-

ever, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the

timer resolution can be increased by software. There are no special cases to consider in the

Normal 8-bit mode, a new counter value can be written anytime. The Output Compare Unit can

be used to generate interrupts at some given time.

11.7.2

Clear Timer on Compare Match (CTC) 8-bit Mode

In Clear Timer on Compare or CTC mode, see Table 11-3 on page 75, the OCR0A Register is

used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the

counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter,

hence also its resolution. This mode allows greater control of the Compare Match output fre-

quency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 11-6. The counter value (TCNT0)

increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter

(TCNT0) is cleared.

Figure 11-6. CTC Mode, Timing Diagram

An interrupt can be generated each time the counter value reaches the TOP value by using the

OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating

the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run-

ning with none or a low prescaler value must be done with care since the CTC mode does not

have the double buffering feature. If the new value written to OCR0A is lower than the current

value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to

its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can

occur. As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle

that the counter counts from MAX to 0x00.

11.7.3

Normal, 16-bit Mode

In 16-bit mode, see Table 11-3 on page 75, the counter (TCNT0H/L) is a incrementing until it

overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the

bottom (0x0000). The Overflow Flag (TOV0) will be set in the same timer clock cycle as the

TCNT0H/L becomes zero. The TOV0 Flag in this case behaves like a 17th bit, except that it is

only set, not cleared. However, combined with the timer overflow interrupt that automatically

clears the TOV0 Flag, the timer resolution can be increased by software. There are no special

cases to consider in the Normal mode, a new counter value can be written anytime. The Output

Compare Unit can be used to generate interrupts at some given time.

TCNTn

OCnx Interrupt Flag Set

Period

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