ATtiny261A datasheet(32/292 Pages) ATMEL

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8197A–AVR–10/09

ATtiny261A/461A/861A

From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the

new clock frequency is active. In this interval, two active clock edges are produced. Here, T1 is

the previous clock period, and T2 is the period corresponding to the new prescaler setting.

6.4

Clock Output Buffer

The device can output the system clock on the CLKO pin. To enable the output, the CKOUT

Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-

cuits on the system. Note that the clock will not be output during reset and the normal operation

of I/O pin will be overridden when the fuse is programmed. Any clock source, including the inter-

nal oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler

is used, it is the divided system clock that is output.

6.5

6.5.1

OSCCAL – Oscillator Calibration Register

• Bits 7:0 – CAL7:0: Oscillator Calibration Value

The Oscillator Calibration Register is used to trim the Calibrated Internal Oscillator to remove

process variations from the oscillator frequency. A pre-programmed calibration value is automat-

ically written to this register during chip reset, giving the Factory calibrated frequency as

specified in Table 19-2 on page 186. The application software can write this register to change

the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table 19-

2 on page 186. Calibration outside that range is not guaranteed.

Note that this oscillator is used to time EEPROM and Flash write accesses, and these write

times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more

than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.

The CAL7:0 bits are used to tune the frequency of the oscillator. A setting of 0x00 gives the low-

est frequency, and a setting of 0xFF gives the highest.

6.5.2

CLKPR – Clock Prescale Register

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE

bit is only updated when the other bits in CLKPR are simultaniosly written to zero. CLKPCE is

cleared by hardware four cycles after it is written or when the CLKPS bits are written. Rewriting

the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the

CLKPCE bit.

• Bits 6:4 – Res: Reserved Bits

These bits are reserved and will always read as zero.

Bit

7654

0x31 (0x51)

CAL7

CAL6

CAL5

CAL4

CAL3

CAL2

CAL1

CAL0

OSCCAL

Read/Write

R/W

Initial Value

Device Specific Calibration Value

Bit

210

0x28 (0x48)

CLKPCE

–

CLKPS3

CLKPS2

CLKPS1

CLKPS0

CLKPR

Read/Write

R/W

Initial Value

See Bit Description

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