ATtiny261A datasheet(17/292 Pages) ATMEL

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8197A–AVR–10/09

ATtiny261A/461A/861A

5.3.1

EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access times for the EEPROM are given in Table 5-1 on page 22. A self-timing func-

tion, however, lets the user software detect when the next byte can be written. If the user code

contains instructions that write the EEPROM, some precautions must be taken. In heavily fil-

tered power supplies, VCC is likely to rise or fall slowly on Power-up/down. This causes the

device for some period of time to run at a voltage lower than specified as minimum for the clock

frequency used. See “Preventing EEPROM Corruption” on page 19 for details on how to avoid

problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to “Atomic Byte Programming” on page 17 and “Split Byte Programming” on page 17 for

details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

5.3.2

Atomic Byte Programming

Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM, the

user must write the address into the EEARL Register and data into EEDR Register. If the

EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is written) will trigger the

erase/write operation. Both the erase and write cycle are done in one operation and the total

programming time is given in Table 5-1 on page 22. The EEPE bit remains set until the erase

and write operations are completed. While the device is busy with programming, it is not possi-

ble to do any other EEPROM operations.

5.3.3

Split Byte Programming

It is possible to split the erase and write cycle in two different operations. This may be useful if

the system requires short access time for some limited period of time (typically if the power sup-

ply voltage falls). In order to take advantage of this method, it is required that the locations to be

written have been erased before the write operation. But since the erase and write operations

are split, it is possible to do the erase operations when the system allows doing time-critical

operations (typically after Power-up).

5.3.4

Erase

To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b01, writing the

EEPE within four cycles after EEMPE is written will trigger the erase operation only (program-

ming time is given in Table 5-1 on page 22). The EEPE bit remains set until the erase operation

completes. While the device is busy programming, it is not possible to do any other EEPROM

operations.

5.3.5

Write

To write a location, the user must write the address into EEAR and the data into EEDR. If the

EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written) will trigger

the write operation only (programming time is given in Table 5-1 on page 22). The EEPE bit

remains set until the write operation completes. If the location to be written has not been erased

before write, the data that is stored must be considered as lost. While the device is busy with

programming, it is not possible to do any other EEPROM operations.

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