ATtiny261A datasheet(37/292 Pages) ATMEL

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8197A–AVR–10/09

ATtiny261A/461A/861A

7.4.5

Watchdog Timer

If the Watchdog Timer is not needed in the application, this module should be turned off. If the

Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume

power. In the deeper sleep modes, this will contribute significantly to the total current consump-

tion. Refer to “Watchdog Timer” on page 42 for details on how to configure the Watchdog Timer.

7.4.6

Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The

most important thing is then to ensure that no pins drive resistive loads. In sleep modes where

both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device

will be disabled. This ensures that no power is consumed by the input logic when not needed. In

some cases, the input logic is needed for detecting wake-up conditions, and it will then be

enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 57 for details on

which pins are enabled. If the input buffer is enabled and the input signal is left floating or has an

analog signal level close to VCC/2, the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal

level close to VCC/2 on an input pin can cause significant current even in active mode. Digital

input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR0, DIDR1).

Refer to “DIDR0 – Digital Input Disable Register 0” on page 159 or “DIDR1 – Digital Input Dis-

able Register 1” on page 159 for details.

7.5

7.5.1

MCUCR – MCU Control Register

The MCU Control Register contains control bits for power management.

• Bit 7 – BODS: BOD Sleep

In order to disable BOD during sleep the BODS bit must be written to logic one. This is controlled

by a timed sequence and the enable bit, BODSE. First, both BODS and BODSE must be set to

one. Second, within four clock cycles, BODS must be set to one and BODSE must be set to

zero. The BODS bit is active three clock cycles after it is set. A sleep instruction must be exe-

cuted while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit

is automatically cleared after three clock cycles.

• Bit 5 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP

instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s

purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of

the SLEEP instruction and to clear it immediately after waking up.

• Bits 4, 3 – SM1:0: Sleep Mode Select Bits 2:0

Bit

7654

0x35 (0x55)

BODS

PUD

SM1

SM0

BODSE

ISC01

ISC00

MCUCR

Read/Write

R/W

Initial Value

0000

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