ATtiny261A datasheet(31/292 Pages) ATMEL

31 / 292 page

8197A–AVR–10/09

ATtiny261A/461A/861A

Notes: 1. These options should only be used when not operating close to the maximum frequency of the

device, and only if frequency stability at start-up is not important for the application. These

options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure frequency stability

at start-up. They can also be used with crystals when not operating close to the maximum fre-

quency of the device, and if frequency stability at start-up is not important for the application.

6.2.7

Default Clock Source

The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default

clock source setting is therefore the Internal Oscillator running at 8 MHz with longest start-up

time and an initial system clock prescaling of 8. This default setting ensures that all users can

make their desired clock source setting using an In-System or High-voltage Programmer.

It should be noted that unprogramming the CKDIV8 fuse may result in overclocking. At low volt-

ages the devices are rated for clock frequencies below that of the internal oscillator. See Section

19.3 on page 185 for maximum operating frequency versus supply voltage.

6.3

System Clock Prescaler

The system clock can be divided by setting the “CLKPR – Clock Prescale Register” on page 32.

This feature can be used to decrease power consumption when the requirement for processing

power is low. This can be used with all clock source options, and it will affect the clock frequency

of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and clkFLASH are divided by a

factor as shown in Table 6-13 on page 33.

6.3.1

Switching Time

When switching between prescaler settings, the System Clock Prescaler ensures that no

glitches occur in the clock system and that no intermediate frequency is higher than neither the

clock frequency corresponding to the previous setting, nor the clock frequency corresponding to

the new setting.

The ripple counter that implements the prescaler runs at the frequency of the undivided clock,

which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the

state of the prescaler – even if it were readable, and the exact time it takes to switch from one

clock division to another cannot be exactly predicted.

1K (1024)CK(2)

14CK + 4 ms

Ceramic resonator,

fast rising power

1K (1024)CK(2)

14CK + 64 ms

Ceramic resonator,

slowly rising power

16K (16384) CK

14CK

Crystal Oscillator,

BOD enabled

16K (16384) CK

14CK + 4 ms

Crystal Oscillator,

fast rising power

16K (16384) CK

14CK + 64 ms

Crystal Oscillator,

slowly rising power

Table 6-12.

Start-up Times for the Crystal Oscillator Clock Selection (Continued)

CKSEL0

SUT1:0

Start-up Time from

Power-down and

Power-save

Additional Delay

from Reset

(VCC = 5.0V)

Recommended Usage

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