ATtiny261A datasheet(42/292 Pages) ATMEL

42 / 292 page

8197A–AVR–10/09

ATtiny261A/461A/861A

8.2.4

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On

the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to

“Watchdog Timer” on page 42 for details on operation of the Watchdog Timer.

Figure 8-6.

Watchdog Reset During Operation

8.3

Internal Voltage Reference

ATtiny261A/461A/861A features an internal bandgap reference. This reference is used for

Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. The

bandgap voltage varies with supply voltage and temperature, as can be seen in Figure 20-45 on

page 217.

8.3.1

Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. The

start-up time is given in “System and Reset Characteristics” on page 187. To save power, the

reference is not always turned on. The reference is on during the following situations:

1. When the BOD is enabled (by programming the BODLEVEL [2:0] Fuse bits).

2. When the bandgap reference is connected to the Analog Comparator (by setting the

ACBG bit in ACSR).

3. When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user

must always allow the reference to start up before the output from the Analog Comparator or

ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three

conditions above to ensure that the reference is turned off before entering Power-down mode.

8.4

Watchdog Timer

The Watchdog Timer is clocked from an on-chip oscillator, which runs at 128 kHz. By controlling

the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table

8-3 on page 47. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The

Watchdog Timer is also reset when it is disabled and when a device reset occurs. Ten different

clock cycle periods can be selected to determine the reset period. If the reset period expires

without another Watchdog Reset, the device resets and executes from the Reset Vector. For

timing details on the Watchdog Reset, refer to Table 8-3 on page 47.

ATtiny261A Scheda tecnica(PDF) 42 Page - ATMEL Corporation