ATtiny261A datasheet(78/292 Pages) ATMEL

78 / 292 page

8197A–AVR–10/09

ATtiny261A/461A/861A

Figure 11-9. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8)

Figure 11-10 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode.

Figure 11-10. Timer/Counter Timing Diagram, CTC mode, with Prescaler (fclk_I/O/8)

11.9 Accessing Registers in 16-bit Mode

In 16-bit mode (the TCW0 bit is set to one) the TCNT0H/L and OCR0A/B or TCNT0L/H and

OCR0B/A are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The

16-bit register must be byte accessed using two read or write operations. The 16-bit

Timer/Counter has a single 8-bit register for temporary storing of the high byte of the 16-bit

access. The same temporary register is shared between all 16-bit registers. Accessing the low

byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is written

by the CPU, the high byte stored in the temporary register, and the low byte written are both cop-

ied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read

by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same

clock cycle as the low byte is read.

There is one exception in the temporary register usage. In the Output Compare mode the 16-bit

Output Compare Register OCR0A/B is read without the temporary register, because the Output

Compare Register contains a fixed value that is only changed by CPU access. However, in 16-

bit Input Capture mode the ICR0 register formed by the OCR0A and OCR0B registers must be

accessed with the temporary register.

To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low

byte must be read before the high byte.

OCFnx

OCRnx

TCNTn

OCRnx Value

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

clk

I/O

clk

(clk

I/O/8)

OCFnx

OCRnx

TCNTn

(CTC)

TOP

TOP - 1

TOP

BOTTOM

BOTTOM + 1

clk

PCK

clk

(clk

PCK /8)

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