MX25L3233F datasheet(6/84 Pages) MCNIX

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MX25L3233F

P/N: PM2113

Rev. 1.6, March 10, 2017

2. GENERAL DESCRIPTION

MX25L3233F is 32Mb bits Serial NOR Flash memory, which is configured as 4,194,304 x 8 internally. When it is

in four I/O mode, the structure becomes 8,388,608 bits x 4. When it is in two I/O mode, the structure becomes

16,777,216 bits x 2.

MX25L3233F features a serial peripheral interface and software protocol allowing operation on a simple 3-wire

bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a

serial data output (SO). Serial access to the device is enabled by CS# input.

MX25L3233F, MXSMIO® (Serial Multi I/O) flash memory, provides sequential read operation on the whole chip

and multi-I/O features.

When it is in quad I/O mode, the SI pin, SO pin, WP# pin and HOLD# pin become SIO0 pin, SIO1 pin, SIO2 pin

and SIO3 pin for address/dummy bits input and data Input/Output.

After program/erase command is issued, auto program/erase algorithms which program/erase and verify the

specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256

bytes) basis. Erase command is executed on 4K-byte sector, 32K-byte/64K-byte block, or whole chip basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status

read command can be issued to detect completion status of a program or erase operation via WIP bit.

When the device is not in operation and CS# is high, it is put in standby mode.

The MX25L3233F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after

100,000 program and erase cycles.

MX25L3233F Scheda tecnica(PDF) 6 Page - Macronix International