MX25L3233F datasheet(41/84 Pages) MCNIX

Il numero della parte	MX25L3233F

Spiegazioni elettronici	3V, 32M-BIT [x 1/x 2/x 4] CMOS MXSMIO짰 (SERIAL MULTI I/O) FLASH MEMORY

PDF	84 Pages

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Produttore elettronici	MCNIX [Macronix International]

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MX25L3233F

P/N: PM2113

Rev. 1.6, March 10, 2017

10-18. Chip Erase (CE)

The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) in-

struction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The

CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.

The sequence of issuing CE instruction is: CS# goes low → sending CE instruction code → CS# goes high.

The SIO[3:1] are don't care.

The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE

timing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the

chip is protected the Chip Erase (CE) instruction will not be executed, but WEL will be reset.

Figure 21. Chip Erase (CE) Sequence (Command 60h or C7h)

34567

60h or C7h

SCLK

CS#

Command

MX25L3233F Scheda tecnica(PDF) 41 Page - Macronix International