MX25L3233F datasheet(24/84 Pages) MCNIX

24 / 84 page

MX25L3233F

P/N: PM2113

Rev. 1.6, March 10, 2017

Status Register

The definition of the status register bits is as below:

WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/

write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write

status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/

write status register cycle.

WEL bit. The Write Enable Latch (WEL) bit is a volatile bit that is set to “1” by the WREN instruction. WEL needs

to be set to “1” before the device can accept program and erase instructions, otherwise the program and erase

instructions are ignored. WEL automatically clears to “0” when a program or erase operation completes. To en-

sure that both WIP and WEL are “0” and the device is ready for the next program or erase operation, it is recom-

mended that WIP be confirmed to be “0” before checking that WEL is also “0”. If a program or erase instruction is

applied to a protected memory area, the instruction will be ignored and WEL will clear to “0”.

BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protect-

ed area (as defined in "Table 1. Protected Area Sizes") of the device to against the program/erase instruction

without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the

Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to

against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase (CE) instructions (only if all

Block Protect bits set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default.

Which is un-protected.

QE bit. The Quad Enable (QE) bit is a non-volatile bit with a factory default of “0”. When QE is “0”, Quad mode

commands are ignored; pins WP#/SIO2 and HOLD#/SIO3 function as WP# and HOLD#, respectively. When QE is “1”,

Quad mode is enabled and Quad mode commands are supported along with Single and Dual mode commands.

Pins WP#/SIO2 and HOLD#/SIO3 function as SIO2 and SIO3, respectively, and their alternate pin functions are

disabled. Enabling Quad mode also disables the HPM and HOLD features.

SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0". SRWD bit is oper-

ated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware pro-

tection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode,

the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block

Protect bits (BP3, BP2, BP1, BP0) are read only. The SRWD bit defaults to be "0".

Table 5. Status Register

Note 1: Please refer to the "Table 1. Protected Area Sizes".

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

SRWD

(status

protect)

(Quad

Enable)

BP3

(level of

protected

block)

BP2

(level of

protected

block)

BP1

(level of

protected

block)

BP0

(level of

protected

block)

WEL

(write enable

latch)

WIP

(write in

progress bit)

1=status

disabled

0=status

enabled

1= Quad

Enable

0=not Quad

Enable

(note 1)

1=write

enable

0=not write

enable

1=write

operation

0=not in write

operation

Non-volatile

bit

Non-volatile

bit

Non-volatile

bit

Non-volatile

bit

Non-volatile

bit

Non-volatile

bit

volatile bit

MX25L3233F Scheda tecnica(PDF) 24 Page - Macronix International

MX25L3233F Scheda tecnica(HTML) 24 Page - Macronix International

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

Scheda tecnica Scarica

Link URL