MX25L3233F datasheet(26/84 Pages) MCNIX

Il numero della parte	MX25L3233F

Spiegazioni elettronici	3V, 32M-BIT [x 1/x 2/x 4] CMOS MXSMIO짰 (SERIAL MULTI I/O) FLASH MEMORY

PDF	84 Pages

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Produttore elettronici	MCNIX [Macronix International]

Homepage	http://www.macronix.com

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MX25L3233F

P/N: PM2113

Rev. 1.6, March 10, 2017

10-6. Write Status Register (WRSR)

The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Be-

fore sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the

Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3,

BP2, BP1, BP0) bits to define the protected area of memory (as shown in "Table 1. Protected Area Sizes"). The

WRSR also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD)

bit in accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of

the status register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is en-

tered.

The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Regis-

ter data on SI→ CS# goes high.

Figure 8. Write Status Register (WRSR) Sequence (Command 01h)

345678 9 10 11 12 13 14 15

Status

Configuration

MSB

SCLK

CS#

01h

High-Z

command

Mode 3

Mode 0

16 17 18 19 20 21 22 23

7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8

MX25L3233F Scheda tecnica(PDF) 26 Page - Macronix International