MX25L3233F datasheet(36/84 Pages) MCNIX

36 / 84 page

MX25L3233F

P/N: PM2113

Rev. 1.6, March 10, 2017

10-13. Performance Enhance Mode

The device could waive the command cycle bits if the two cycle bits after address cycle toggles. (Please note

"Figure 16. 4 x I/O Read enhance performance Mode Sequence (Command EBh) (SPI Mode)")

Performance enhance mode is supported for 4READ mode.

“EBh” commands support enhance mode.

After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low

of the first clock as address instead of command cycle.

To exit enhance mode, a new fast read command whose first two dummy cycles is not toggle then exit. Or issue

”FFh” data cycles to exit enhance mode.

Figure 16. 4 x I/O Read enhance performance Mode Sequence (Command EBh) (SPI Mode)

High Impedance

345678

SCLK

SI/SIO0

SO/SIO1

CS#

10 11

13 14

EBh

address

bit20, bit16..bit0

address

bit21, bit17..bit1

P4 P0

P5 P1

P6 P2

P7 P3

data

bit4, bit0, bit4....

data

bit5 bit1, bit5....

15 16

n+1

...........

......

...........

n+7

n+9

n+13

17 18 19 20 21 22 23

High Impedance

WP#/SIO2

address

bit22, bit18..bit2

data

bit6 bit2, bit6....

High Impedance

HOLD#/SIO3

address

bit23, bit19..bit3

data

bit7 bit3, bit7....

8 Bit Instruction

6 Address cycles

Performance

enhance

indicator (Note1)

Data Output

SCLK

SI/SIO0

SO/SIO1

CS#

address

bit20, bit16..bit0

address

bit21, bit17..bit1

P4 P0

P5 P1

P6 P2

P7 P3

data

bit4, bit0, bit4....

data

bit5 bit1, bit5....

WP#/SIO2

address

bit22, bit18..bit2

data

bit6 bit2, bit6....

HOLD#/SIO3

address

bit23, bit19..bit3

data

bit7 bit3, bit7....

6 Address cycles

Performance

enhance

indicator (Note1)

Data Output

Congurable

Dummy cycles

(Note 2)

Congurable

Dummy cycles

(Note 2)

Note:

1. Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F, if not using

performance enhance recommend to keep 1 or 0 in performance enhance indicator.

Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF.

2. The Configurable Dummy Cycle is set by Configuration Register Bit. Please see "Dummy Cycle and

Frequency Table"

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