MX25L3233F datasheet(34/84 Pages) MCNIX

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MX25L3233F

P/N: PM2113

Rev. 1.6, March 10, 2017

10-12. 4 x I/O Read Mode (4READ)

The 4READ instruction enables quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of

status Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge

of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum

frequency fQ. The first address byte can be at any location. The address is automatically increased to the next

higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ in-

struction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ

instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit.

The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address in-

terleave on SIO3, SIO2, SIO1 & SIO0→2+4 dummy cycles (default) →data out interleave on SIO3, SIO2, SIO1

& SIO0→ to end 4READ operation can use CS# to high at any time during data out. (Please refer to the figure

below)

Figure 15. 4 x I/O Read Mode Sequence (Command EBh)

High Impedance

345678

SCLK

SI/SIO0

SO/SIO1

CS#

10 11

13 14

EBh

address

bit20, bit16..bit0

address

bit21, bit17..bit1

P4 P0

P5 P1

P6 P2

P7 P3

data

bit4, bit0, bit4....

data

bit5 bit1, bit5....

15 16 17 18 19 20 21 22 23

High Impedance

WP#/SIO2

address

bit22, bit18..bit2

data

bit6 bit2, bit6....

High Impedance

HOLD#/SIO3

address

bit23, bit19..bit3

data

bit7 bit3, bit7....

8 Bit Instruction

6 Address cycles

Performance

enhance indicator

(Note 1 & 2)

Data Output

Configurable

Dummy cycles

(Note 3)

Notes:

1. Hi-impedance is inhibited for the two clock cycles.

2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.

3. The Configurable Dummy Cycle is set by Configuration Register Bit. Please see "Dummy Cycle and Fre-

quency Table"

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