MX25L3233F datasheet(32/84 Pages) MCNIX

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MX25L3233F

P/N: PM2113

Rev. 1.6, March 10, 2017

10-10. 2 x I/O Read Mode (2READ)

The 2READ instruction enables Double Transfer Rate of Serial NOR Flash in read mode. The address is latched

on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK

at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased

to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single

2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writ-

ing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.

The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address in-

terleave on SIO1 & SIO0→ 4 dummy cycles(default) on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to

end 2READ operation can use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any

impact on the Program/Erase/Write Status Register current cycle.

Figure 13. 2 x I/O Read Mode Sequence (Command BBh)

High Impedance

345678

SCLK

SI/SIO0

SO/SIO1

CS#

18 19 20

BB(hex)

21 22 23 24 25 26 27 28 29

D6 D4

D7 D5

Command

12 ADD Cycle

Configurable

Dummy cycles

A22 A20

A2 A0

A3 A1

A23 A21

…

Data Out

Note: SI/SIO0 or SO/SIO1 should be kept "0h" or "Fh" in the first two dummy cycles. In other words, P2=P0 or

P3=P1 is necessary.

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