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MX25L3233F Scheda tecnica(PDF) 74 Page - Macronix International

Il numero della parte MX25L3233F
Spiegazioni elettronici  3V, 32M-BIT [x 1/x 2/x 4] CMOS MXSMIO짰 (SERIAL MULTI I/O) FLASH MEMORY
PDF  84 Pages
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Produttore elettronici  MCNIX [Macronix International]
Homepage  http://www.macronix.com
Logo MCNIX - Macronix International

MX25L3233F Scheda tecnica(HTML) 74 Page - Macronix International

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MX25L3233F
P/N: PM2113
Rev. 1.6, March 10, 2017
14-1. Initial Delivery State
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
Figure 50. Power Up/Down and Voltage Drop
Table 19. Power-Up/Down Voltage and Timing
VCC
Time
VCC (max.)
VCC (min.)
V
tPWD
tVSL
Chip Select is not allowed
Full Device
Access
Allowed
PWD (max.)
When powering down the device, VCC must drop below VPWD for at least tPWD to ensure the device will initialize
correctly during power up. Please refer to "Figure 50. Power Up/Down and Voltage Drop" and "Table 19. Power-
Up/Down Voltage and Timing" below for more details.
Note: These parameters are characterized only.
Symbol Parameter
Min.
Max.
Unit
tVSL
VCC(min.) to device operation
800
us
VWI
Write Inhibit Voltage
1.5
2.5
V
VPWD
VCC voltage needed to below VPWD for ensuring initialization will occur
0.9
V
tPWD
The minimum duration for ensuring initialization will occur
300
us
VCC
VCC Power Supply
2.65
3.6
V



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