MX25L3233F datasheet(35/84 Pages) MCNIX

35 / 84 page

MX25L3233F

P/N: PM2113

Rev. 1.6, March 10, 2017

Another sequence of issuing 4READ instruction especially useful in random access is: CS# goes low→send

4READ instruction→3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0→performance enhance toggling

bit P[7:0]→4 dummy cycles →data out until CS# goes high → CS# goes low (The following 4READ instruction is

not allowed, hence 8 cycles of 4READ can be saved comparing to normal 4READ mode) → 24-bit random ac-

cess address (Please refer to "Figure 16. 4 x I/O Read enhance performance Mode Sequence (Command EBh) (SPI

Mode)" ).

In the performance-enhancing mode (Notes of "Figure 16. 4 x I/O Read enhance performance Mode Sequence

(Command EBh) (SPI Mode)"), P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can

make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0];

likewise P[7:0]=FFh, 00h, AAh or 55h. These commands will reset the performance enhance mode. And after-

wards CS# is raised and then lowered, the system then will return to normal operation.

While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any im-

pact on the Program/Erase/Write Status Register current cycle.

MX25L3233F Scheda tecnica(PDF) 35 Page - Macronix International