MX25L3233F datasheet(25/84 Pages) MCNIX

25 / 84 page

MX25L3233F

P/N: PM2113

Rev. 1.6, March 10, 2017

Configuration Register

The Configuration Register is able to change the default status of Flash memory. Flash memory will be configured

after the CR bit is set.

ODS bit

The output driver strength ODS bit are volatile bits, which indicate the output driver level of the device. The

Output Driver Strength is defaulted=1 when delivered from factory. To write the ODS bit requires the Write Status

TB bit

The Top/Bottom (TB) bit is a OTP bit. The Top/Bottom (TB) bit is used to configure the Block Protect area by BP

bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as “0”, which

means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory device.

To write the TB bit requires the Write Status Register (WRSR) instruction to be executed.

Table 6. Configuration Register

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Reserved

(Dummy

Cycle)

Reserved

(top/bottom

selected)

Reserved

ODS

2READ/

4READ

Dummy

Cycle

0=Top area

protect

1=Bottom

area protect

(Default=0)

0, Output driver

strength=1

1, Output driver

strength=1/4

(Default=0)

volatile

OTP

volatile

Note: Refer to "Table 7. Dummy Cycle and Frequency Table", with "Don't Care" on other Reserved Configuration

Registers.

Numbers of Dummy

Cycles

Freq. (MHz)

2READ

0 (default)

104

133

4READ

0 (default)

104

133

Table 7. Dummy Cycle and Frequency Table

MX25L3233F Scheda tecnica(PDF) 25 Page - Macronix International

MX25L3233F Scheda tecnica(HTML) 25 Page - Macronix International

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

Scheda tecnica Scarica

Link URL