MX25L3233F datasheet(64/84 Pages) MCNIX

Il numero della parte	MX25L3233F

Spiegazioni elettronici	3V, 32M-BIT [x 1/x 2/x 4] CMOS MXSMIO짰 (SERIAL MULTI I/O) FLASH MEMORY

PDF	84 Pages

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Produttore elettronici	MCNIX [Macronix International]

Homepage	http://www.macronix.com

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64 / 84 page

MX25L3233F

P/N: PM2113

Rev. 1.6, March 10, 2017

11. POWER-ON STATE

The device is at the following states after power-up:

- Standby mode

- Write Enable Latch (WEL) bit is reset

The device must not be selected during power-up and power-down stage until the VCC reaches the following

levels:

- VCC minimum at power-up stage and then after a delay of tVSL

- GND at power-down

Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.

An internal Power-on Reset (POR) circuit may protect the device from data corruption and inadvertent data

change during power up state.

For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is

not guaranteed. The read, write, erase, and program command should be sent after the time delay:

- tVSL after VCC reached VCC minimum level

The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.

Note:

- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommend-

ed. (generally around 0.1uF)

MX25L3233F Scheda tecnica(PDF) 64 Page - Macronix International