MX25L3233F datasheet(69/84 Pages) MCNIX

69 / 84 page

MX25L3233F

P/N: PM2113

Rev. 1.6, March 10, 2017

Notes:

1. tCH + tCL must be greater than or equal to 1/ fC.

2. The value guaranteed by characterization, not 100% tested in production.

3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

4. Latency time is required to complete Erase/Program Suspend operation until WIP bit is "0".

5. For tPRS, minimum timing must be observed before issuing the next program suspend command.

However, a period equal to or longer than the typical timing is required in order for the program operation

to make progress.

6. For tERS, minimum timing must be observed before issuing the next erase suspend command.

However, a period equal to or longer than the typical timing is required in order for the erase operation to

make progress.

Symbol Alt. Parameter

Min.

Typ.

Max. Unit

tRCR

Recovery Time from Read

tRCP

Recovery Time from Program

tRCE

Recovery Time from Erase

tDP

CS# High to Deep Power-down Mode

tRES1

CS# High to Standby Mode without Electronic Signature

Read

100

tRES2

CS# High to Standby Mode with Electronic Signature Read

100

Write Status Register Cycle Time

tBP

Byte-Program

tPP

Page Program Cycle Time

0.33

1.2

tSE

Sector Erase Cycle Time (4KB)

200

tBE32K

Block Erase Cycle Time (32KB)

0.14

0.6

tBE

Block Erase Cycle Time (64KB)

0.25

tCE

Chip Erase Cycle Time

tWSR

Write Security Register Time

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