MX25L3233F datasheet(31/84 Pages) MCNIX

31 / 84 page

MX25L3233F

P/N: PM2113

Rev. 1.6, March 10, 2017

10-9. Dual Read Mode (DREAD)

The DREAD instruction enable double throughput of Serial NOR Flash in read mode. The address is latched on

rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at

a maximum frequency fT. The first address byte can be at any location. The address is automatically increased

to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single

DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writ-

ing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit.

The sequence of issuing DREAD instruction is: CS# goes low → sending DREAD instruction → 3-byte address

on SI → 8-bit dummy cycle → data out interleave on SO1 & SO0 → to end DREAD operation can use CS# to

high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any im-

pact on the Program/Erase/Write Status Register current cycle.

Figure 12. Dual Read Mode Sequence (Command 3Bh)

High Impedance

345678

SCLK

SI/SIO0

SO/SIO1

CS#

30 31 32

39 40 41

43 44 45

D6 D4

D7 D5

Command

24 ADD Cycle

8 dummy

cycle

A23 A22

A1 A0

…

Data Out

MX25L3233F Scheda tecnica(PDF) 31 Page - Macronix International