MX25L3233F datasheet(33/84 Pages) MCNIX

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MX25L3233F

P/N: PM2113

Rev. 1.6, March 10, 2017

10-11. Quad Read Mode (QREAD)

The QREAD instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of

status Register must be set to "1" before sending the QREAD instruction. The address is latched on rising edge

of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum

frequency fQ. The first address byte can be at any location. The address is automatically increased to the next

higher address after each byte data is shifted out, so the whole memory can be read out at a single QREAD in-

struction. The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD

instruction, the following data out will perform as 4-bit instead of previous 1-bit.

The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte address

on SI → 8-bit dummy cycle → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QREAD operation can

use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any im-

pact on the Program/Erase/Write Status Register current cycle.

Figure 14. Quad Read Mode Sequence (Command 6Bh)

High Impedance

345678

SCLK

SI/SIO0

SO/SIO1

CS#

30 31 32 33

38 39 40 41 42

High Impedance

WP#/SIO2

High Impedance

HOLD#/SIO3

8 dummy cycles

D4 D0

D5 D1

D6 D2

D7 D3

D4 D0

D5 D1

D6 D2

D7 D3

A23 A22

A2 A1 A0

Command

24 ADD Cycles

Data

Out 1

Data

Out 2

Data

Out 3

…

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