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R7FA2L1AB2DFN Scheda tecnica(PDF) 101 Page - Renesas Technology Corp |
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R7FA2L1AB2DFN Scheda tecnica(HTML) 101 Page - Renesas Technology Corp |
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101 / 110 page  Table 3.4 Register description (9 of 15) Peripheral name Dim Dim inc. Dim index Register name Description Address offset Size R/W Reset value Reset mask ADC12 — — — ADCMPANSER A/D Compare Function Window A Extended Input Select Register 0x092 8 R/W 0x00 0xFF ADC12 — — — ADCMPLER A/D Compare Function Window A Extended Input Comparison Condition Setting Register 0x093 8 R/W 0x00 0xFF ADC12 — — — ADCMPANSR0 A/D Compare Function Window A Channel Select Register 0 0x094 16 R/W 0x0000 0xFFFF ADC12 — — — ADCMPANSR1 A/D Compare Function Window A Channel Select Register 1 0x096 16 R/W 0x0000 0xFFFF ADC12 — — — ADCMPLR0 A/D Compare Function Window A Comparison Condition Setting Register 0 0x098 16 R/W 0x0000 0xFFFF ADC12 — — — ADCMPLR1 A/D Compare Function Window A Comparison Condition Setting Register 1 0x09A 16 R/W 0x0000 0xFFFF ADC12 2 0x2 0-1 ADCMPDR%s A/D Compare Function Window A Lower- Side/Upper-Side Level Setting Register 0x09C 16 R/W 0x0000 0xFFFF ADC12 — — — ADCMPSR0 A/D Compare Function Window A Channel Status Register 0 0x0A0 16 R/W 0x0000 0xFFFF ADC12 — — — ADCMPSR1 A/D Compare Function Window A Channel Status Register1 0x0A2 16 R/W 0x0000 0xFFFF ADC12 — — — ADCMPSER A/D Compare Function Window A Extended Input Channel Status Register 0x0A4 8 R/W 0x00 0xFF ADC12 — — — ADCMPBNSR A/D Compare Function Window B Channel Select Register 0x0A6 8 R/W 0x00 0xFF ADC12 — — — ADWINLLB A/D Compare Function Window B Lower- Side/Upper-Side Level Setting Register 0x0A8 16 R/W 0x0000 0xFFFF ADC12 — — — ADWINULB A/D Compare Function Window B Lower- Side/Upper-Side Level Setting Register 0x0AA 16 R/W 0x0000 0xFFFF ADC12 — — — ADCMPBSR A/D Compare Function Window B Status Register 0x0AC 8 R/W 0x00 0xFF ADC12 — — — ADSSTRL A/D Sampling State Register 0x0DD 8 R/W 0x0D 0xFF ADC12 — — — ADSSTRT A/D Sampling State Register 0x0DE 8 R/W 0x0D 0xFF ADC12 — — — ADSSTRO A/D Sampling State Register 0x0DF 8 R/W 0x0D 0xFF ADC12 15 0x1 0-14 ADSSTR%s A/D Sampling State Register 0x0E0 8 R/W 0x0D 0xFF DAC12 — — — DADR0 D/A Data Register 0 0x00 16 R/W 0x0000 0xFFFF DAC12 — — — DACR D/A Control Register 0x04 8 R/W 0x1F 0xFF DAC12 — — — DADPR DADR0 Format Select Register 0x05 8 R/W 0x00 0xFF DAC12 — — — DAADSCR D/A A/D Synchronous Start Control Register 0x06 8 R/W 0x00 0xFF DAC12 — — — DAVREFCR D/A VREF Control Register 0x07 8 R/W 0x00 0xFF SCI0 — — — SMR Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x00 8 R/W 0x00 0xFF SCI0 — — — SMR_SMCI Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1) 0x00 8 R/W 0x00 0xFF SCI0 — — — BRR Bit Rate Register 0x01 8 R/W 0xFF 0xFF SCI0 — — — SCR Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) 0x02 8 R/W 0x00 0xFF SCI0 — — — SCR_SMCI Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1) 0x02 8 R/W 0x00 0xFF SCI0 — — — TDR Transmit Data Register 0x03 8 R/W 0xFF 0xFF SCI0 — — — SSR Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0 and FCR.FM = 0) 0x04 8 R/W 0x84 0xFF SCI0 — — — SSR_FIFO Serial Status Register for Non-Smart Card Interface and FIFO Mode (SCMR.SMIF = 0 and FCR.FM = 1) 0x04 8 R/W 0x80 0xFD RA2L1 Datasheet Appendix 3. I/O Registers R01DS0385EJ0100 Rev.1.00 Aug 06, 2020 Page 101 of 110 |
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