AT83SND1CXXX-ROTIL datasheet(64/212 Pages) ATMEL

64 / 212 page

4109J–8051–10/06

AT8xC51SND1C

consisting of data request and data acknowledgment is implemented. Each time the MP3

decoder needs MP3 data, it sets the MPREQ, MPFREQ and MPBREQ flags respectively in

MP3STA and MP3STA1 registers. MPREQ flag can generate an interrupt if enabled as

explained in Section “Interrupt”. The CPU must then load data in the buffer by writing it through

MP3DAT register thus acknowledging the previous request. As shown in Figure 12-2, the

MPFREQ flag remains set while data (i.e a frame) is requested by the decoder. It is cleared

when no more data is requested and set again when new data are requested. MPBREQ flag

toggles at every Byte writing.

Note:

1. The first request after enable, consists in 1024 Bytes of data to fill in the input buffer.

Figure 12-2. Data Timing Diagram

12.1.3

MP3 Clock

The MP3 decoder clock is generated by division of the PLL clock. The division factor is given by

MPCD4:0 bits in MP3CLK register. Figure 12-3 shows the MP3 decoder clock generator and its

calculation formula. The MP3 decoder clock frequency depends only on the incoming MP3

frames.

Figure 12-3. MP3 Clock Generator and Symbol

As soon as the frame header has been decoded and the MPEG version extracted, the minimum

MP3 input frequency must be programmed according to Table 58.

Table 58. MP3 Clock Frequency

12.2

Audio Controls

12.2.1

Volume Control

The MP3 decoder implements volume control on both right and left channels. The MP3VOR and

MP3VOL registers allow a 32-step volume control according to Table 59.

MPFREQ Flag

MPBREQ Flag

MPREQ Flag

Cleared when Reading MP3STA

Write to MP3DAT

MPEG Version

Minimum MP3 Clock (MHz)

I21

10.5

MPCD4:0

MP3CLK

MP3 Decoder Clock

MP3clk

PLL clk

MPCD

----------------------------

MP3

CLOCK

MP3 Clock Symbol

PLL

CLOCK

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