AT83SND1CXXX-ROTIL datasheet(100/212 Pages) ATMEL

100 / 212 page

100

4109J–8051–10/06

AT8xC51SND1C

Reset Value = 0001 0000b

Table 84. UEPNUM Register

UEPNUM (S:C7h) – USB Endpoint Number

Reset Value = 0000 0000b

Table 85. UEPCONX Register

UEPCONX (S:D4h) – USB Endpoint X Control Register (X = EPNUM set in UEPNUM)

Bit

Number

Bit

Mnemonic

Description

7 - 6

Reserved

The value read from these bits is always 0. Do not set these bits.

5EWUPCPU

Wake Up CPU Interrupt Enable Bit

Set to enable the Wake Up CPU interrupt.

Clear to disable the Wake Up CPU interrupt.

4EEOFINT

End Of Reset Interrupt Enable Bit

Set to enable the End Of Reset interrupt. This bit is set after reset.

Clear to disable End Of Reset interrupt.

3ESOFINT

Start Of Frame Interrupt Enable Bit

Set to enable the SOF interrupt.

Clear to disable the SOF interrupt.

2 - 1

Reserved

The value read from these bits is always 0. Do not set these bits.

0ESPINT

Suspend Interrupt Enable Bit

Set to enable Suspend interrupt.

Clear to disable Suspend interrupt.

7654

3210

------

EPNUM1

EPNUM0

Bit

Number

Bit

Mnemonic

Description

7 - 2

Reserved

The value read from these bits is always 0. Do not set these bits.

1 - 0

EPNUM1:0

Endpoint Number Bits

Set this field with the number of the endpoint which should be accessed when

reading or writing to registers UEPSTAX, UEPDATX, UBYCTX or UEPCONX.

7654

3210

EPEN

NAKIEN

NAKOUT

NAKIN

DTGL

EPDIR

EPTYPE1

EPTYPE0

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