AT83SND1CXXX-ROTIL datasheet(26/212 Pages) ATMEL

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4109J–8051–10/06

AT8xC51SND1C

The next 16 Bytes above the register banks form a block of bit-addressable memory space. The

C51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this

area can be directly addressed by these instructions. The bit addresses in this area are 00h to

7Fh.

Figure 9. Lower 128 Bytes Internal RAM Organization

6.1.2

Upper 128 Bytes RAM

The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect

addressing mode.

6.1.3

Expanded RAM

The on-chip 2K Bytes of expanded RAM (ERAM) are accessible from address 0000h to 07FFh

using indirect addressing mode through MOVX instructions. In this address range, EXTRAM bit

in AUXR register (see Table 19) is used to select the ERAM (default) or the XRAM. As shown in

Figure 8 when EXTRAM = 0, the ERAM is selected and when EXTRAM = 1, the XRAM is

selected (see Section “External Space”).

The ERAM memory can be resized using XRS1:0 bits in AUXR register to dynamically increase

external access to the XRAM space. Table 16 details the selected ERAM size and address

range.

Table 16. ERAM Size Selection

Note:

Lower 128 Bytes RAM, Upper 128 Bytes RAM, and expanded RAM are made of volatile memory

cells. This means that the RAM content is indeterminate after power-up and must then be initial-

ized properly.

6.2

External Space

6.2.1

Memory Interface

The external memory interface comprises the external bus (port 0 and port 2) as well as the bus

control signals (RD, WR, and ALE).

Bit-Addressable Space

4 Banks of

8 Registers

R0-R7

30h

7Fh

(Bit Addresses 0-7Fh)

20h

2Fh

18h

1Fh

10h

17h

08h

0Fh

00h

07h

XRS1

XRS0

ERAM Size

Address

256 Bytes

0 to 00FFh

512 Bytes

0 to 01FFh

1K Byte

0 to 03FFh

2K Bytes

0 to 07FFh

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