AT83SND1CXXX-ROTIL datasheet(41/212 Pages) ATMEL

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4109J–8051–10/06

AT8xC51SND1C

8.2

External Interrupts

8.2.1

INT1:0 Inputs

External interrupts INT0 and INT1 (INTn, n = 0 or 1) pins may each be programmed to be level-

triggered or edge-triggered, dependent upon bits IT0 and IT1 (ITn, n = 0 or 1) in TCON register

as shown in Figure 8-2. If ITn = 0, INTn is triggered by a low level at the pin. If ITn = 1, INTn is

negative-edge triggered. External interrupts are enabled with bits EX0 and EX1 (EXn, n = 0 or 1)

in IEN0. Events on INTn set the interrupt request flag IEn in TCON register. If the interrupt is

edge-triggered, the request flag is cleared by hardware when vectoring to the interrupt service

routine. If the interrupt is level-triggered, the interrupt service routine must clear the request flag

and the interrupt must be deasserted before the end of the interrupt service routine.

INT0 and INT1 inputs provide both the capability to exit from Power-down mode on low level sig-

nals as detailed in section “Exiting Power-down Mode”, page 50.

Figure 8-2.

INT1:0 Input Circuitry

8.2.2

KIN3:0 Inputs

External interrupts KIN0 to KIN3 provide the capability to connect a matrix keyboard. For

detailed information on these inputs, refer to section “Keyboard Interface”, page 178.

8.2.3

Input Sampling

External interrupt pins (INT1:0 and KIN3:0) are sampled once per peripheral cycle (6 peripheral

clock periods) (see Figure 8-3). A level-triggered interrupt pin held low or high for more than 6

peripheral clock periods (12 oscillator in standard mode or 6 oscillator clock periods in X2 mode)

guarantees detection. Edge-triggered external interrupts must hold the request pin low for at

least 6 peripheral clock periods.

Figure 8-3.

Minimum Pulse Timings

INT0/1

IT0/1

TCON.0/2

EX0/1

IEN0.0/2

INT0/1

Interrupt

Request

IE0/1

TCON.1/3

Edge-Triggered Interrupt

Level-Triggered Interrupt

1 cycle

> 1 Peripheral Cycle

1 cycle

> 1 Peripheral Cycle

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