AT83SND1CXXX-ROTIL datasheet(12/212 Pages) ATMEL

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4109J–8051–10/06

AT8xC51SND1C

Clock Controller

The AT8xC51SND1C clock controller is based on an on-chip oscillator feeding an on-chip Phase

Lock Loop (PLL). All internal clocks to the peripherals and CPU core are generated by this

controller.

5.1

Oscillator

The AT8xC51SND1C X1 and X2 pins are the input and the output of a single-stage on-chip

inverter (see Figure 5-1) that can be configured with off-chip components such as a Pierce oscil-

lator (see Figure 5-2). Value of capacitors and crystal characteristics are detailed in the

Section “DC Characteristics”, page 163.

The oscillator outputs three different clocks: a clock for the PLL, a clock for the CPU core, and a

clock for the peripherals as shown in Figure 5-1. These clocks are either enabled or disabled,

depending on the power reduction mode as detailed in the section “Power Management” on

page 47. The peripheral clock is used to generate the Timer 0, Timer 1, MMC, ADC, SPI, and

Port sampling clocks.

Figure 5-1.

Oscillator Block Diagram and Symbol

Figure 5-2.

Crystal Connection

5.2

X2 Feature

Unlike standard C51 products that require 12 oscillator clock periods per machine cycle, the

AT8xC51SND1C need only 6 oscillator clock periods per machine cycle. This feature called the

“X2 feature” can be enabled using the X2 bit(1) in CKCON (see Table 16) and allows the

AT8xC51SND1C to operate in 6 or 12 oscillator clock periods per machine cycle. As shown in

Figure 5-1, both CPU and peripheral clocks are affected by this feature. Figure 5-3 shows the X2

mode switching waveforms. After reset the standard mode is activated. In standard mode the

CPU and peripheral clock frequency is the oscillator frequency divided by 2 while in X2 mode, it

PCON.1

IDL

PCON.0

Peripheral

CPU Core

CKCON.0

÷ 2

PER

CLOCK

Clock

Peripheral Clock Symbol

CPU

CLOCK

CPU Core Clock Symbol

OSC

CLOCK

Oscillator Clock Symbol

Oscillator

Clock

VSS

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