AT83SND1CXXX-ROTIL datasheet(73/212 Pages) ATMEL

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4109J–8051–10/06

AT8xC51SND1C

13. Audio Output Interface

The AT8xC51SND1C implement an audio output interface allowing the audio bitstream to be

output in various formats. It is compatible with right and left justification PCM and I2S formats

and thanks to the on-chip PLL (see Section “Clock Controller”, page 12) allows connection of

almost all of the commercial audio DAC families available on the market.

The audio bitstream can be from 2 different types:

•

The MP3 decoded bitstream coming from the MP3 decoder for playing songs.

•

The audio bitstream coming from the MCU for outputting voice or sounds.

13.1

Description

The C51 core interfaces to the audio interface through five special function registers: AUDCON0

and AUDCON1, the Audio Control registers (see Table 74 and Table 75); AUDSTA, the Audio

Status register (see Table 76); AUDDAT, the Audio Data register (see Table 77); and AUDCLK,

the Audio Clock Divider register (see Table 78).

Figure 13-1 shows the audio interface block diagram, blocks are detailed in the following

sections.

Figure 13-1. Audio Interface Block Diagram

13.2

Clock Generator

The audio interface clock is generated by division of the PLL clock. The division factor is given

by AUCD4:0 bits in CLKAUD register. Figure 13-2 shows the audio interface clock generator

AUD

CLOCK

UDRN

AUDSTA.6

DSIZ

AUDCON0.1

DSEL

Clock Generator

DCLK

DOUT

SCLK

JUST4:0

AUDCON0.7:3

POL

AUDCON0.2

AUDEN

AUDCON1.0

HLR

AUDCON0.0

SRC

AUDCON1.7

Data Converter

Audio Data

From C51

Audio Data

From MP3

DUP1:0

AUDCON1.2:1

SREQ

AUDSTA.7

Audio Buffer

AUBUSY

AUDSTA.5

Data Ready

DRQEN

AUDCON1.6

MP3 Buffer

Decoder

Sample

Request To

MP3 Decoder

AUDDAT

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