AT83SND1CXXX-ROTIL datasheet(38/212 Pages) ATMEL

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4109J–8051–10/06

AT8xC51SND1C

Interrupt System

The AT8xC51SND1C, like other control-oriented computer architectures, employ a program

interrupt method. This operation branches to a subroutine and performs some service in

response to the interrupt. When the subroutine completes, execution resumes at the point where

the interrupt occurred. Interrupts may occur as a result of internal AT8xC51SND1C activity (e.g.,

timer overflow) or at the initiation of electrical signals external to the microcontroller (e.g., key-

board). In all cases, interrupt operation is programmed by the system designer, who determines

priority of interrupt service relative to normal code execution and other interrupt service routines.

All of the interrupt sources are enabled or disabled by the system designer and may be manipu-

lated dynamically.

A typical interrupt event chain occurs as follows:

•

An internal or external device initiates an interrupt-request signal. The AT8xC51SND1C,

latches this event into a flag buffer.

•

The priority of the flag is compared to the priority of other interrupts by the interrupt handler.

A high priority causes the handler to set an interrupt flag.

•

This signals the instruction execution unit to execute a context switch. This context switch

breaks the current flow of instruction sequences. The execution unit completes the current

instruction prior to a save of the program counter (PC) and reloads the PC with the start

address of a software service routine.

•

The software service routine executes assigned tasks and as a final activity performs a RETI

(return from interrupt) instruction. This instruction signals completion of the interrupt, resets

the interrupt-in-progress priority and reloads the program counter. Program operation then

continues from the original point of interruption.

Table 38. Interrupt System Signals

Six interrupt registers are used to control the interrupt system. 2 8-bit registers are used to

enable separately the interrupt sources: IEN0 and IEN1 registers (see Table 41 and Table 42).

Four 8-bit registers are used to establish the priority level of the different sources: IPH0, IPL0,

IPH1 and IPL1 registers (see Table 43 to Table 46).

8.1

Interrupt System Priorities

Each of the interrupt sources on the AT8xC51SND1C can be individually programmed to one of

four priority levels. This is accomplished by one bit in the Interrupt Priority High registers (IPH0

and IPH1) and one bit in the Interrupt Priority Low registers (IPL0 and IPL1). This provides each

interrupt source four possible priority levels according to Table 39.

Signal

Name

Type

Description

Alternate

Function

INT0

External Interrupt 0

See section "External Interrupts", page 41.

P3.2

INT1

External Interrupt 1

See section “External Interrupts”, page 41.

P3.3

KIN3:0

Keyboard Interrupt Inputs

See section “Keyboard Interface”, page 178.

P1.3:0

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