AT83SND1CXXX-ROTIL datasheet(15/212 Pages) ATMEL

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4109J–8051–10/06

AT8xC51SND1C

5.4

Registers

Table 16. CKCON Register

CKCON (S:8Fh) – Clock Control Register

Reset Value = 0000 000Xb (AT89C51SND1C) or 0000 0000b (AT83SND1C)

Table 17. PLLCON Register

PLLCON (S:E9h) – PLL Control Register

765

43210

TWIX2

WDX2

SIX2

T1X2

T0X2

Bit

Number

Bit

Mnemonic

Description

7TWIX2

Two-Wire Clock Control Bit

Set to select the oscillator clock divided by 2 as TWI clock input (X2

independent).

Clear to select the peripheral clock as TWI clock input (X2 dependent).

6WDX2

Watchdog Clock Control Bit

Set to select the oscillator clock divided by 2 as watchdog clock input (X2

independent).

Clear to select the peripheral clock as watchdog clock input (X2 dependent).

Reserved

The values read from this bit is indeterminate. Do not set this bit.

4SIX2

Enhanced UART Clock (Mode 0 and 2) Control Bit

Set to select the oscillator clock divided by 2 as UART clock input (X2

independent).

Clear to select the peripheral clock as UART clock input (X2 dependent)..

Reserved

The values read from this bit is indeterminate. Do not set this bit.

2T1X2

Timer 1 Clock Control Bit

Set to select the oscillator clock divided by 2 as timer 1 clock input (X2

independent).

Clear to select the peripheral clock as timer 1 clock input (X2 dependent).

1T0X2

Timer 0 Clock Control Bit

Set to select the oscillator clock divided by 2 as timer 0 clock input (X2

independent).

Clear to select the peripheral clock as timer 0 clock input (X2 dependent).

0X2

System Clock Control Bit

Clear to select 12 clock periods per machine cycle (STD mode, FCPU = FPER =

OSC/2).

Set to select 6 clock periods per machine cycle (X2 mode, F

CPU = FPER = FOSC).

765

43210

PLLRES

PLLEN

PLOCK

Bit

Number

Bit

Mnemonic

Description

7 - 6

R1:0

PLL Least Significant Bits R Divider

2 LSB of the 10-bit R divider.

5 - 4

Reserved

The values read from these bits are always 0. Do not set these bits.

PLLRES

PLL Reset Bit

Set this bit to reset the PLL.

Clear this bit to free the PLL and allow enabling.

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