AT83SND1CXXX-ROTIL datasheet(87/212 Pages) ATMEL

87 / 212 page

4109J–8051–10/06

AT8xC51SND1C

is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has to be

read.

When all the endpoint FIFO Bytes have been read, the firmware should clear the RXOUTB0 bit

to allow the USB controller to accept the next OUT packet on this endpoint. Until the RXOUTB0

bit has been cleared by the firmware, the USB controller will answer a NAK handshake for each

OUT requests.

If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data won’t be

stored, but the USB controller will consider that the packet is valid if the CRC is correct and the

endpoint Byte counter contains the number of Bytes sent by the Host.

14.4.2

Bulk/Interrupt OUT Transactions in Ping-pong Mode

Figure 14-10. Bulk/Interrupt OUT Transactions in Ping-pong Mode

An endpoint should be first enabled and configured before being able to receive Bulk or Interrupt

packets.

When a valid OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by the

USB controller. This triggers an interrupt if enabled. The firmware has to select the correspond-

ing endpoint, store the number of data Bytes by reading the UBYCTX register. If the received

packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has

to be read.

When all the endpoint FIFO Bytes have been read, the firmware should clear the RXOUB0 bit to

allow the USB controller to accept the next OUT packet on the endpoint bank 0. This action

switches the endpoint bank 0 and 1. Until the RXOUTB0 bit has been cleared by the firmware,

the USB controller will answer a NAK handshake for each OUT requests on the bank 0 endpoint

FIFO.

When a new valid OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is set by

the USB controller. This triggers an interrupt if enabled. The firmware empties the bank 1 end-

OUT

DATA0 (n Bytes)

ACK

HOST

UFI

C51

Endpoint FIFO bank 0 - Read Byte 1

RXOUTB0

Endpoint FIFO bank 0 - Read Byte 2

Endpoint FIFO bank 0 - Read Byte n

Clear RXOUTB0

OUT

DATA1 (m Bytes)

ACK

RXOUTB1

Endpoint FIFO bank 1 - Read Byte 1

Endpoint FIFO bank 1 - Read Byte 2

Endpoint FIFO bank 1 - Read Byte m

Clear RXOUTB1

OUT

DATA0 (p Bytes)

ACK

RXOUTB0

Endpoint FIFO bank 0 - Read Byte 1

Endpoint FIFO bank 0 - Read Byte 2

Endpoint FIFO bank 0 - Read Byte p

Clear RXOUTB0

AT83SND1CXXX-ROTIL Scheda tecnica(PDF) 87 Page - ATMEL Corporation

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