AT83SND1CXXX-ROTIL datasheet(56/212 Pages) ATMEL

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4109J–8051–10/06

AT8xC51SND1C

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When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit (TR1).

For this situation, use Timer 1 only for applications that do not require an interrupt (such as a

Baud Rate Generator for the Serial Port) and switch Timer 1 in and out of mode 3 to turn it

off and on.

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It is important to stop the Timer/Counter before changing modes.

10.4.1

Mode 0 (13-bit Timer)

Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 register)

with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register (see Figure 10-

2). The upper 3 bits of TL1 register are ignored. Prescaler overflow increments TH1 register.

10.4.2

Mode 1 (16-bit Timer)

Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in cascade

(see Figure 10-4). The selected input increments TL1 register.

10.4.3

Mode 2 (8-bit Timer with Auto-Reload)

Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from TH1 reg-

ister on overflow (see Figure 10-6). TL1 overflow sets TF1 flag in TCON register and reloads

TL1 with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged.

10.4.4

Mode 3 (Halt)

Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt Timer 1

when TR1 run control bit is not available i.e. when Timer 0 is in mode 3.

10.5

Interrupt

Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This flag is

set every time an overflow occurs. Flags are cleared when vectoring to the Timer interrupt rou-

tine. Interrupts are enabled by setting ETx bit in IEN0 register. This assumes interrupts are

globally enabled by setting EA bit in IEN0 register.

Figure 10-10. Timer Interrupt System

10.6

Registers

Table 50. TCON Register

TCON (S:88h) – Timer/Counter Control Register

TF0

TCON.5

ET0

IEN0.1

Timer 0

Interrupt Request

TF1

TCON.7

ET1

IEN0.3

Timer 1

Interrupt Request

7654

3210

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

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