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AT83SND1CXXX-ROTIL Scheda tecnica(PDF) 27 Page - ATMEL Corporation |
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AT83SND1CXXX-ROTIL Scheda tecnica(HTML) 27 Page - ATMEL Corporation |
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27 / 212 page ![]() 27 4109J–8051–10/06 AT8xC51SND1C Figure 10 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 17 describes the exter- nal memory interface signals. Figure 10. External Data Memory Interface Structure Table 17. External Data Memory Interface Signals 6.2.2 Page Access Mode The AT8xC51SND1C implement a feature called Page Access that disables the output of DPH on P2 when executing MOVX @DPTR instruction. Page Access is enable by setting the DPH- DIS bit in AUXR register. Page Access is useful when application uses both ERAM and 256 Bytes of XRAM. In this case, software modifies intensively EXTRAM bit to select access to ERAM or XRAM and must save it if used in interrupt service routine. Page Access allows external access above 00FFh address without generating DPH on P2. Thus ERAM is accessed using MOVX @Ri or MOVX @DPTR with DPTR < 0100h, < 0200h, < 0400h or < 0800h depending on the XRS1:0 bits value. Then XRAM is accessed using MOVX @DPTR with DPTR ≥ 0800h regardless of XRS1:0 bits value while keeping P2 for general I/O usage. 6.2.3 External Bus Cycles This section describes the bus cycles the AT8xC51SND1C executes to read (see Figure 11), and write data (see Figure 12) in the external data memory. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock period Signal Name Type Description Alternate Function A15:8 O Address Lines Upper address lines for the external bus. P2.7:0 AD7:0 I/O Address/Data Lines Multiplexed lower address lines and data for the external memory. P0.7:0 ALE O Address Latch Enable ALE signals indicates that valid address information are available on lines AD7:0. - RD O Read Read signal output to external data memory. P3.7 WR O Write Write signal output to external memory. P3.6 RAM PERIPHERAL AT8xC51SND1C P2 P0 AD7:0 A15:8 A7:0 A15:8 D7:0 A7:0 ALE WR OE RD WR Latch |
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