AT83SND1CXXX-ROTIL datasheet(93/212 Pages) ATMEL

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4109J–8051–10/06

AT8xC51SND1C

Important note: when a Clear Halt Feature occurs for an endpoint, the firmware should reset this

endpoint using the UEPRST resgister in order to reset the data toggle management.

14.7.3

Start of Frame Detection

The SOFINT bit in the USBINT register is set when the USB controller detects a Start Of Frame

PID. This triggers an interrupt if enabled. The firmware should clear the SOFINT bit to allow the

next Start of Frame detection.

14.7.4

Frame Number

When receiving a Start Of Frame, the frame number is automatically stored in the UFNUML and

UFNUMH registers. The CRCOK and CRCERR bits indicate if the CRC of the last Start Of

Frame is valid (CRCOK set at 1) or corrupted (CRCERR set at 1). The UFNUML and UFNUMH

registers are automatically updated when receiving a new Start of Frame.

14.7.5

Data Toggle Bit

The Data Toggle bit is set by hardware when a DATA0 packet is received and accepted by the

USB controller and cleared by hardware when a DATA1 packet is received and accepted by the

USB controller. This bit is reset when the firmware resets the endpoint FIFO using the UEPRST

For Control endpoints, each SETUP transaction starts with a DATA0 and data toggling is then

used as for Bulk endpoints until the end of the Data stage (for a control write transfer). The Sta-

tus stage completes the data transfer with a DATA1 (for a control read transfer).

For Isochronous endpoints, the device firmware should ignore the data-toggle.

14.8

Suspend/Resume Management

14.8.1

Suspend

The Suspend state can be detected by the USB controller if all the clocks are enabled and if the

USB controller is enabled. The bit SPINT is set by hardware when an idle state is detected for

more than 3 ms. This triggers a USB interrupt if enabled.

In order to reduce current consumption, the firmware can put the USB PAD in idle mode, stop

the clocks and put the C51 in Idle or Power-down mode. The Resume detection is still active.

The USB PAD is put in idle mode when the firmware clear the SPINT bit. In order to avoid a new

suspend detection 3ms later, the firmware has to disable the USB clock input using the SUSP-

CLK bit in the USBCON Register. The USB PAD automatically exits of idle mode when a wake-

up event is detected.

The stop of the 48 MHz clock from the PLL should be done in the following order:

Disable of the 48 MHz clock input of the USB controller by setting to 1 the SUSPCLK bit

in the USBCON register.

Disable the PLL by clearing the PLLEN bit in the PLLCON register.

14.8.2

Resume

When the USB controller is in Suspend state, the Resume detection is active even if all the

clocks are disabled and if the C51 is in Idle or Power-down mode. The WUPCPU bit is set by

hardware when a non-idle state occurs on the USB bus. This triggers an interrupt if enabled.

This interrupt wakes up the CPU from its Idle or Power-down state and the interrupt function is

then executed. The firmware will first enable the 48 MHz generation and then reset to 0 the

SUSPCLK bit in the USBCON register if needed.

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