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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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AT83SND1CXXX-ROTIL Scheda tecnica(PDF) 96 Page - ATMEL Corporation |
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AT83SND1CXXX-ROTIL Scheda tecnica(HTML) 96 Page - ATMEL Corporation |
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96 / 212 page  96 4109J–8051–10/06 AT8xC51SND1C Table 1. Priority Levels 14.9.2 USB Interrupt Control System As shown in Figure 14-16, many events can produce a USB interrupt: • TXCMPL: Transmitted In Data (Table 86 on page 101). This bit is set by hardware when the Host accept a In packet. • RXOUTB0: Received Out Data Bank 0 (Table 86 on page 101). This bit is set by hardware when an Out packet is accepted by the endpoint and stored in bank 0. • RXOUTB1: Received Out Data Bank 1 (only for Ping-pong endpoints) (Table 86 on page 101). This bit is set by hardware when an Out packet is accepted by the endpoint and stored in bank 1. • RXSETUP: Received Setup (Table 86 on page 101). This bit is set by hardware when an SETUP packet is accepted by the endpoint. • STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints) (Table 86 on page 101). This bit is set by hardware when a STALL handshake has been sent as requested by STALLRQ, and is reset by hardware when a SETUP packet is received. • SOFINT: Start of Frame Interrupt (Table 82 on page 99). This bit is set by hardware when a USB start of frame packet has been received. • WUPCPU: Wake-Up CPU Interrupt (Table 82 on page 99). This bit is set by hardware when a USB resume is detected on the USB bus, after a SUSPEND state. • SPINT: Suspend Interrupt (Table 82 on page 99). This bit is set by hardware when a USB suspend is detected on the USB bus. IPHUSB IPLUSB USB Priority Level 0 0 0..................Lowest 01 1 10 2 1 1 3..................Highest |
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