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AT83SND1CXXX-ROTIL Scheda tecnica(PDF) 81 Page - ATMEL Corporation |
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AT83SND1CXXX-ROTIL Scheda tecnica(HTML) 81 Page - ATMEL Corporation |
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81 / 212 page ![]() 81 4109J–8051–10/06 AT8xC51SND1C Figure 14-3 shows how to connect the AT8xC51SND1C to the USB connector. D+ and D- pins are connected through 2 termination resistors. A pull-up resistor is implemented on D+ to inform the host of a full speed device connection. Value of these resistors is detailed in the section “DC Characteristics”. Figure 14-1. USB Device Controller Block Diagram Figure 14-2. USB Connection 14.1.1 Clock Controller The USB controller clock is generated by division of the PLL clock. The division factor is given by USBCD1:0 bits in USBCLK register (see Table 94). Figure 14-3 shows the USB controller clock generator and its calculation formula. The USB controller clock frequency must always be 48 MHz. Figure 14-3. USB Clock Generator and Symbol 14.1.2 Serial Interface Engine (SIE) The SIE performs the following functions: • NRZI data encoding and decoding. USB CLOCK 48 MHz 12 MHz D+ D- DPLL SIE UFI USB Buffer To/From C51 Core D+ D- VBUS GND D+ D- VSS To Power R USB RUSB VDD Supply R FS USBCD1:0 USBCLK 48 MHz USB Clock USBclk PLLclk USBCD 1 + -------------------------------- = USB CLOCK USB Clock Symbol PLL CLOCK |
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