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AT83SND1CXXX-ROTIL Scheda tecnica(PDF) 83 Page - ATMEL Corporation

Il numero della parte AT83SND1CXXX-ROTIL
Spiegazioni elettronici  Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
PDF  212 Pages
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Produttore elettronici  ATMEL [ATMEL Corporation]
Homepage  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT83SND1CXXX-ROTIL Scheda tecnica(HTML) 83 Page - ATMEL Corporation

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83
4109J–8051–10/06
AT8xC51SND1C
Figure 14-5. UFI Block Diagram
Figure 14-6. USB Typical Transaction Load
14.2
Configuration
14.2.1
General Configuration
•
USB controller enable
Before any USB transaction, the 48 MHz required by the USB controller must be correctly
generated (See “Clock Controller” on page 19).
The USB controller should be then enabled by setting the EUSB bit in the USBCON register.
•
Set address
After a Reset or a USB reset, the software has to set the FEN (Function Enable) bit in the
USBADDR register. This action will allow the USB controller to answer to the requests sent
at the address 0.
When a SET_ADDRESS request has been received, the USB controller must only answer
to the address defined by the request. The new address should be stored in the USBADDR
register. The FEN bit and the FADDEN bit in the USBCON register should be set to allow
the USB controller to answer only to requests sent at the new address.
To/From C51 Core
Endpoint Control
C51 side
Endpoint Control
USB side
Endpoint 2
Endpoint 1
Endpoint 0
USBCON
USBINT
USBIEN
UEPINT
UEPIEN
UEPNUM
UEPSTAX
USBADDR
UEPCONX
UEPDATX
UEPRST
UBYCTX
UFNUMH
UFNUML
Asynchronous Information
Transfer
Control
FSM
To/From SIE
12 MHz DPLL
OUT Transactions:
HOST
UFI
C51
OUT
DATA0 (n Bytes)
ACK
Endpoint FIFO read (n Bytes)
OUT
DATA1
NACK
OUT
DATA1
ACK
IN Transactions:
HOST
UFI
C51
IN
ACK
Endpoint FIFO Write
IN
DATA1
NACK
C51 interrupt
IN
DATA1
C51 interrupt
Endpoint FIFO write



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