ADIN1300CCPZ-R7 datasheet(24/96 Pages) AD

24 / 96 page

Data Sheet

ADIN1300

THEORY OF OPERATION

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Rev. B | 24 of 96

The RESET_N pin is referenced to the AVDD3P3 voltage domain.

In applications where the reset signal is originating from a device

operating with VDDIO residing in a 1.8 V voltage domain, use a

level shifter to translate the reset signal to meet the input voltage

thresholds of the RESET_N pin.

When the RESET_N pin is deasserted, the crystal oscillator circuit

is enabled and the clock is given time to stabilize. The state of

the hardware configuration pins is read and latched, the digital and

analog circuits are initialized, and the PHY core clock multiplier unit

(CMU) is reset. After 5 ms from the deassertion of RESET_N, the

management interface registers are accessible and the device can

be programmed. This time is significantly shorter if a single-ended

clock rather than a crystal is used and the management interface

registers are accessible 3 ms after the deassertion of RESET_N.

If the ADIN1300 is configured to enter software power-down after

a reset (see Table 25), the ADIN1300 enters software power-down

mode and an interrupt is generated to indicate that a hardware

reset occurred.

The following events occur after a hardware reset:

►

The crystal oscillator circuit is enabled and time is allowed for the

clock to stabilize.

►

The hardware configuration pins are read and the values latch-

ed. These set the default values of the pin-dependent registers in

the subsystem and PHY core registers.

►

The MAC interface block is reset.

►

The PHY core is reset.

►

The PHY core CMU is reset.

►

An interrupt to indicate that a hardware reset occurred is gen-

erated depending on the pin configuration, if the ADIN1300

was configured to enter software power-down mode after reset.

Clearing the interrupt on INT_N after this condition can be per-

formed by reading the GE_IRQ_LAT register at address 0xFF1E.

or reading the IRQ_STATUS register at Address 0x0019.

Software Reset

The ADIN1300 supports the following different software resets that

reset specific circuit blocks under software control:

►

Subsystem software reset with pin configuration

►

Subsystem software reset

►

PHY core software reset

Subsystem Software Reset with Pin

Configuration

The ADIN1300 supports a software reset capability that behaves in

a similar way to a hardware reset (see Table 20 and the Subsystem

ration can be initiated by setting the GE_SFT_ RST_CFG_EN bit

(Address 0xFF0D) to 1 before setting GE_SFT_RST bit (Address

0xFF0C) to 1. This subsystem software reset follows the same

reset sequence as the POR and hardware reset, except the crystal

oscillator is not disabled and the clock stabilization step is skipped.

The state of the hardware configuration pins is read and latched.

These configuration pins set the default values of the pin dependent

registers in the subsystem and PHY core registers. The MAC

interface block and PHY core are reset. If a 125 MHz clock is

selected as the PHY output clock, the GP_CLK pin, the PHY core

CMU is not reset. Otherwise, the CMU is reset. The main difference

between this type of reset and a hardware reset is that the crystal

oscillator is not disabled.

Note that the GE_SFT_RST_CFG_EN bit is reset to its default

value of 0 by this type of reset.

The following events occur after a subsystem software reset with

pin configuration:

►

The crystal oscillator circuit is not disabled during this type of

reset.

►

The hardware configuration pins are read and the values latch-

ed. These set the default values of the pin dependent registers in

the subsystem and PHY core registers.

►

The MAC interface block is reset.

►

The PHY core is reset.

►

The PHY core CMU is reset.

►

The output reference clock is not available on the CLK25_REF

pin during this reset.

►

If a 125 MHz clock is selected as the PHY output clock it is not

available on the GP_CLK pin during this reset.

Subsystem Software Reset

The subsystem can be reset by setting the GE_SFT_RST bit,

Address 0xFF0C to 1. This bit is self clearing. Setting this bit resets

the subsystem and PHY core registers, the MAC interface block,

and the PHY core. The hardware configuration pins are not reread,

and previously latched values of the hardware configuration pins

are used to set the default values of the pin dependent registers in

the subsystem and PHY core registers.

The following events occur after a subsystem software reset:

►

The crystal oscillator circuit is not disabled during this type of

reset.

►

The hardware configuration pins are not reread. The pin depend-

ent registers in the subsystem registers and PHY core registers

are reset to the default values defined by the previously latched

values of the hardware configuration pins.

►

The MAC interface block is reset.

►

The PHY core is reset.

►

If a 125 MHz clock is selected as the PHY output clock, the

GP_CLK pin, the PHY core CMU is not reset. Otherwise, the

CMU is reset.

►

The output reference clock (if enabled) is available on the

CLK25_REF pin during this reset.

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