ADIN1300CCPZ-R7 datasheet(56/96 Pages) AD

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Data Sheet

ADIN1300

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Rev. B | 56 of 96

Table 42. Bit Descriptions for MSTR_SLV_CONTROL (Continued)

Bits

Bit Name

Description

Reset

Access

101: reserved.

100: Test Mode 4—transmitter distortion test.

011: Test Mode 3—transmit jitter test in slave mode.

010: Test Mode 2—transmit jitter test in master mode.

001: Test Mode 1—transmit waveform test.

000: normal operation.

MAN_MSTR_SLV_EN_ADV

Manual Master/Slave Enable Advertisement Bit.

0x0

R/W

1: enable master slave manual configuration value.

0: disable master slave manual configuration value.

MAN_MSTR_ADV

Master/Slave Advertisement Bit.

0x0

R/W

1: configure PHY as master during master slave negotiation only when

MAN_MSTR_SLV_EN_ADV is set to Logical 1.

0: configure PHY as slave during master slave negotiation only when MAN_MSTR_SLV_EN_ADV

is set to Logical 1.

PREF_MSTR_ADV

Prefer Master (or Port Type) Advertisement Bit. This bit is used to indicate the preference to oper-

ate as master (multiport device) or as slave (single port device) if the MAN_MSTR_SLV_EN_ADV

bit (Bit 9), is not set. Usage of this bit is described in Clause 40.5.2 of IEEE Standard 802.3. Note

that the default value of this register bit is configurable via the hardware configuration pins, which

allows the default operation of the PHY to be configured in unmanaged applications.

0x0

R/W

1: multiport device.

0: single port device.

FD_1000_ADV

1000BASE-T Full Duplex Advertisement Bit. Note that the default value of this register bit is

configurable via the hardware configuration pins, which allows the default operation of the PHY to

be configured in unmanaged applications.

0x1

R/W

1: advertise PHY is 1000BASE-T full duplex capable.

0: advertise PHY is not 1000BASE-T full duplex capable.

HD_1000_ADV

1000BASE-T Half Duplex Advertisement Bit. Note that the default value of this register bit is

configurable via the hardware configuration pins, which allows the default operation of the PHY to

be configured in unmanaged applications.

0x0

R/W

1: advertise PHY is 1000BASE-T half duplex capable.

0: advertise PHY is not 1000BASE-T half duplex capable.

[7:0]

RESERVED

Reserved.

0x0

Master Slave Status Register

Address: 0x000A, Reset: 0x0000, Name: MSTR_SLV_STATUS

This address corresponds to the master slave status register specified in Clause 40.5.1.1 of IEEE Standard 802.3.

Table 43. Bit Descriptions for MSTR_SLV_STATUS

Bits

Bit Name

Description

Reset

Access

MSTR_SLV_FLT

Master/Slave Configuration Fault Bit. When this bit goes high, it latches high until it is unlatched by reading.

This bit self clears on autonegotiation enable or autonegotiation complete. See Clause 40.5.1.1 of IEEE

Standard 802.3 for more details.

0x0

R LH SC

1: master slave configuration fault detected.

0: no master slave configuration fault detected.

MSTR_RSLVD

Master/Slave Configuration Resolution Bit.

0x0

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