ADIN1300CCPZ-R7 datasheet(60/96 Pages) AD

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Data Sheet

ADIN1300

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Rev. B | 60 of 96

Table 50. Bit Descriptions for PHY_CTRL_STATUS_2 (Continued)

Bits

Bit Name

Description

Reset

Access

power-down mode. Note that the default value of this register bit is configurable via the hardware configuration

pins. This allows the default operation of the PHY to be configured in unmanaged applications.

1: enable periodic transmission of the pulse while in energy detect power-down mode.

0: disable periodic transmission of the pulse while in energy detect power-down mode.

PHY_IN_NRG_PD

This status bit indicates that the PHY is in energy detect power-down mode.

0x0

1: PHY is in energy detect power-down mode.

0: PHY is not in energy detect power-down mode.

RESERVED

Reserved.

0x0

R/W

PHY Control 2 Register

Address: 0x0016, Reset: 0x0308, Name: PHY_CTRL_2

This register provides access to various PHY control registers, for control of clocking, group MDIO access, and autonegotiation.

Table 51. Bit Descriptions for PHY_CTRL_2

Bits

Bit Name

Description

Reset

Access

HD_TX_CRS_EN

When set, this register indicates that the PHY must assert CRS on transmit in half duplex mode.

0x0

R/W

[14:12]

RESERVED

Reserved.

0x0

R/W

DN_SPEED_TO_100_EN

Setting this bit enables downspeed to 100BASE-TX. Note that autonegotiation must also be enabled.

If the PHY is unable to bring a link up at 1000BASE-T, it automatically drops down to 100BASE-TX

(assuming this speed has been advertised). Note that the default value of this register bit is configura-

ble via the hardware configuration pins performing the PHY_CFG1 and PHY_CFG0 functions, which

allows the default operation of the PHY to be configured in unmanaged applications.

0x0

R/W

1: enable downspeed to 100BASE-TX.

0: disable downspeed to 100BASE-TX.

DN_SPEED_TO_10_EN

Setting this bit enables downspeed to 10BASE-T. Note that autonegotiation must also be enabled.

If the PHY is unable to bring a link up at a high speed, it automatically drops down to 10BASE-T

(assuming this speed has been advertised) if necessary.

0x0

R/W

1: enable downspeed to 10BASE-T.

0: disable downspeed to 10BASE-T.

[9:7]

RESERVED

Reserved.

0x6

R/W

GROUP_MDIO_EN

The group MDIO enable register bit may be used to place the PHY in group MDIO mode. In this mode,

the PHY responds to any write or address operation to PHY address 5'd31 as if it was an access to its

own PHY address. It is recommended that this bit be set only when performing specific sequences and

then be cleared again.

0x0

R/W

[5:4]

RESERVED

Reserved.

0x0

R/W

[3:1]

CLK_CNTRL

The clock control bit allows the desired speed of the TX_CLK and RX_CLK signals to be specified

when the link is down and allows the desired speed of the TX_CLK signal to be specified when a

1000BASE-T link is active. In each case the choices of speed are off, 2.5 MHz and 25 MHz. The

default value of 3b100 specifies 2.5 MHz in all cases.

Provided to allow users to control the TX_CLK and RX_CLK speed, but to always provide a clock

to the MAC, using lower speed clock can have benefit of lower power operation. For majority of

application use cases, the default setting is the appropriate setting to use. Some MACs require a

TX_CLK clock when the link is down, others can support no TX_CLK when there is no link or a Gigabit

link is established and can use this control bit to reduce power consumption.

0x4

R/W

RESERVED

RESERVED.

0x0

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